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-- Company: 
-- Engineer:
--
-- Create Date:   17:20:57 11/23/2017
-- Design Name:   
-- Module Name:   F:/miaobiao/s_t.vhd
-- Project Name:  miaobiao
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: save
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY s_t IS
END s_t;
 
ARCHITECTURE behavior OF s_t IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT save
    PORT(
         key : IN  std_logic;
         clr : IN  std_logic;
         hi1 : IN  std_logic_vector(3 downto 0);
         hi0 : IN  std_logic_vector(3 downto 0);
         mi1 : IN  std_logic_vector(3 downto 0);
         mi0 : IN  std_logic_vector(3 downto 0);
         si1 : IN  std_logic_vector(3 downto 0);
         si0 : IN  std_logic_vector(3 downto 0);
         ho1 : OUT  std_logic_vector(3 downto 0);
         ho0 : OUT  std_logic_vector(3 downto 0);
         mo1 : OUT  std_logic_vector(3 downto 0);
         mo0 : OUT  std_logic_vector(3 downto 0);
         so1 : OUT  std_logic_vector(3 downto 0);
         so0 : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal key : std_logic := '0';
   signal clr : std_logic := '0';
   signal hi1 : std_logic_vector(3 downto 0) := (others => '0');
   signal hi0 : std_logic_vector(3 downto 0) := (others => '0');
   signal mi1 : std_logic_vector(3 downto 0) := (others => '0');
   signal mi0 : std_logic_vector(3 downto 0) := (others => '0');
   signal si1 : std_logic_vector(3 downto 0) := (others => '0');
   signal si0 : std_logic_vector(3 downto 0) := (others => '0');

 	--Outputs
   signal ho1 : std_logic_vector(3 downto 0);
   signal ho0 : std_logic_vector(3 downto 0);
   signal mo1 : std_logic_vector(3 downto 0);
   signal mo0 : std_logic_vector(3 downto 0);
   signal so1 : std_logic_vector(3 downto 0);
   signal so0 : std_logic_vector(3 downto 0);
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
   constant <clock>_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: save PORT MAP (
          key => key,
          clr => clr,
          hi1 => hi1,
          hi0 => hi0,
          mi1 => mi1,
          mi0 => mi0,
          si1 => si1,
          si0 => si0,
          ho1 => ho1,
          ho0 => ho0,
          mo1 => mo1,
          mo0 => mo0,
          so1 => so1,
          so0 => so0
        );

   -- Clock process definitions
   <clock>_process :process
   begin
		<clock> <= '0';
		wait for <clock>_period/2;
		<clock> <= '1';
		wait for <clock>_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for <clock>_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;
